Handbook of Digital Techniques for High Speed Design: Design Examples, Signaling and Memory Technologies, Fiber Optics, Modeling and Simulation to Signal Integrity

Part - 1: Introduction Trends in High Speed Design ASICs, Backplane Configurations, and SerDes Technology A Few Basic son Signal Integrity Signaling Technologies and Devices Gunning Transceiver Logic (GTL, GTLP, GTL+, AGTL+) Low Voltage Differential Signaling (LVDS) Bus LVDS (BLVDS), LVDS Multipoint (LVDM), and Multipoint LVDS (M-LVDS) High Speed Transceiver Logic (HSTL) and Stub Series Terminated Logic (SSTL) Emitter Coupled Logic (ECL, PECL, LVPECL, ECLinPS Lite and Plus, SiGe, ECL Pro, GigaPro and GigaComm) Current Mode Logic (CML) FPGAs - 11.1 Gbps RocketIOs and HardCopy Devices Fiber Optic Components High Speed Interconnects and Cabling High Speed Memory and Memory Interfaces Memory Devoices Overview and Memory Signaling Technologies Double Data Rate SDRAM (DDR, DDR2) and SPICE Simulation GDDR3, ZBT, FCRAM, SigmaRAM, RLDRAM, DDR SRAM, Flash, FeRAM, and MRAM Quad Data Rate (QDR, QDRII) SRAM Direct Rambus DRAM (DRDRAM) Xtreme Data Rate (XDR) DRAM, FlexPhase and ODR Modeling, Simulation, and EDA Tools Time Domain Reflectometry (TDR), Time Domain Transmission (TDT), and VNAs Modeling with IBIS Mentor Graphics - EDA Tools for High-Speed Design, simulation, Verification, and Layout Design Concepts and Examples Advances in Design, Modeling, Simulation, and Measurement Validation of High Performance Board to Board 5 to 10 Gbps Interconnects Appendix 23.4 Generalized N Port, Mixed-Mode S-Parameters IBIS Modeling and Simulation of High-Speed Fiber-Optic Transceivers Designing with LVDS Designing to 10 Gbps Using SerDes Transceivers, Serializers, and Deserializers WarpLink SerDes System Design Example Emerging Protocols and Technologies Electrical Optical Circuit Board (EOCB) RapidIO PCI Express and ExpressCard Lab and Instrumentation Electrical and Optical Test Equipment