Novel Defect Modeling and Development of ATPG For combinational QCA Circuits (Record no. 115918)
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| 000 -LEADER | |
|---|---|
| fixed length control field | ngm a22 7a 4500 |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION | |
| fixed length control field | 190222b ||||| |||| 00| 0 eng d |
| 082 ## - DEWEY DECIMAL CLASSIFICATION NUMBER | |
| Classification number | TT000067 |
| Item number | DHA |
| 100 ## - MAIN ENTRY--PERSONAL NAME | |
| Personal name | Dhare, Vaishali Hitesh |
| 245 ## - TITLE STATEMENT | |
| Title | Novel Defect Modeling and Development of ATPG For combinational QCA Circuits |
| Statement of responsibility, etc | by Vaishali Hitesh Dhare |
| 260 ## - PUBLICATION, DISTRIBUTION, ETC. (IMPRINT) | |
| Place of publication, distribution, etc | Ahmedabad |
| Name of publisher, distributor, etc | Nirma Institute of Technology |
| Date of publication, distribution, etc | 2018 |
| 300 ## - PHYSICAL DESCRIPTION | |
| Extent | 170p Ph. D. Thesis with Synopsis and CD |
| 500 ## - GENERAL NOTE | |
| General note | Guided by: Dr. Usha Sandeep Mehta With Synopsis and CD 13EXTPHDE102<br/><br/>ABSTRACT:<br/>Although the current Complementary Metal Oxide Semiconductor (CMOS) silicon<br/>technology is ruling the semiconductor industry for almost four and half decades, the<br/>scaling of it will reach its fundamental limit in the near future. As a result, several<br/>new devices for computation are being explored to extend the historical IC scaling<br/>and to sustain the performance gain beyond CMOS scaling. The International Technology<br/>Roadmap for Semiconductors (ITRS) 2015 describes the \Beyond CMOS" in<br/>length and according to it, Quantum-dot Cellular Automata (QCA) is the transistor<br/>less computation paradigm and viable candidate for next generation device technology.<br/>Since QCA has extremely small geometry; at molecular scale, it is very natural<br/>that this technology may have more and dierent manufacturing defects and faults<br/>compared to the existing CMOS technology. Hence, whatever defect types and fault<br/>models are available in CMOS technology, beyond that, new types of defects and<br/>corresponding new fault models will be necessary to test such circuits. Further, advanced<br/>algorithms for test generation including this new fault models are required to<br/>be developed.<br/>In this work, the basics of QCA, its implementation, fabrication and basic devices<br/>are studied. Also, QCA related possible defects are surveyed, studied and analyzed<br/>using existing QCA tools at the logic and layout level. Similar to CMOS IC technology,<br/>QCA circuit implementation also requires a mature set of Electronic Design<br/>Automation (EDA) tools like simulator, synthesizer etc. Therefore, available QCA<br/>tools for dierent abstraction levels of design are studied. It is perceived that, no open<br/>source and low cost commercial synthesis tools are available. Considering synthesis<br/>as important process and requirement of synthesized QCA circuits for further test<br/>development, synthesis method: QSynthesizer is proposed.<br/>It is observed that the QCA defects like cell missing, additional cell, cell misalignment cell displacement and cell rotation aects the functionality of QCA devices. The<br/>literature is available for Single Missing Cell (SMC) defect. Here, the novel Multiple<br/>Missing Cells (MMC) defect modeling is proposed and its corresponding stuck at<br/>fault sets are identied and it is shown that these faults are not covered by SMC fault<br/>models. The proposed defect modeling is backed by the extensive simulation and<br/>kink energy based mathematical analysis. Further, Hardware Description Language<br/>(HDL)-Verilog model for QCA devices are developed to activate the fault models<br/>caused by the MMC defect at the logic level.<br/>Further, testing properties are proposed for the fault models caused by the MMC<br/>defect in main QCA logic primitive Majority Voter (MV), MV as AND (MV AND)<br/>and MV as OR (MV OR) gates to make test generation process easy and ecient.<br/>The test vector set of conventional stuck at faults is not sucient to detect the faults<br/>caused by the MMC defect. Therefore, both the fault models are considered in this<br/>work for the test generation. Further, Sandia Controllability and Observability Analysis<br/>Program (SCOAP) testability measures for MV is extended for MV based circuits<br/>which is further used for decision making in test pattern generator algorithms. The<br/>extension of basic Automatic Test Pattern Generator (ATPG) specifically targeting<br/>QCA MV properties is proposed. Subsequently, extended FAN (A Fanout Oriented)<br/>based ATPG for combinational QCA circuits: FANQ is proposed which detects the<br/>conventional s-a-0, s-a-1, fault models related to SMC as well as MMC. The proposed<br/>FANQ ATPG uses the MV specic testing properties and extended testability measures.<br/>The Hamming distance based compaction is performed to reduce the number<br/>of test vectors. At last, generated test vectors by FANQ ATPG are validated at layout<br/>level to confirm the detection of multiple missing cells defect. |
| 856 ## - ELECTRONIC LOCATION AND ACCESS | |
| Uniform Resource Identifier | http://repository.nirmauni.ac.in/jspui/handle/123456789/8360 |
| Public note | Institute Repository (Campus Access) |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) | |
| Source of classification or shelving scheme | Dewey Decimal Classification |
| Koha item type | Thesis |
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