Cryptographic Hardware and Embedded Systems: CHES 2006 (Record no. 117138)
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| 000 -LEADER | |
|---|---|
| fixed length control field | nam a22 4500 |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION | |
| fixed length control field | 190921b ||||| |||| 00| 0 eng d |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| International Standard Book Number | 9783540465591 |
| 082 ## - DEWEY DECIMAL CLASSIFICATION NUMBER | |
| Classification number | 005.8 |
| Item number | CRY |
| 245 ## - TITLE STATEMENT | |
| Title | Cryptographic Hardware and Embedded Systems: CHES 2006 |
| 260 ## - PUBLICATION, DISTRIBUTION, ETC. (IMPRINT) | |
| Name of publisher, distributor, etc | Springer |
| Place of publication, distribution, etc | Germany |
| Date of publication, distribution, etc | 2006 |
| 300 ## - PHYSICAL DESCRIPTION | |
| Extent | 462p |
| 500 ## - GENERAL NOTE | |
| General note | Template Attacks in Principal Subspaces<br/>Templates vs. Stochastic Methods<br/>Towards Security Limits in Side-Channel Attacks<br/>HIGHT: A New Block Cipher Suitable for Low-Resource Device<br/>Integer Factoring Utilizing PC Cluster<br/>Optically Enhanced Position-Locked Power Analysis<br/>Pinpointing the Side-Channel Leakage of Masked AES Hardware Implementations<br/>A Generalized Method of Differential Fault Attack Against AES Cryptosystem<br/>Breaking Ciphers with COPACOBANA –A Cost-Optimized Parallel Code Breaker<br/>Implementing the Elliptic Curve Method of Factoring in Reconfigurable Hardware<br/>Implementing Cryptographic Pairings on Smartcards<br/>SPA-Resistant Scalar Multiplication on Hyperelliptic Curve Cryptosystems Combining Divisor Decomposition Technique and Joint Regular Form<br/>Fast Generation of Prime Numbers on Portable Devices: An Update<br/>A Proposition for Correlation Power Analysis Enhancement<br/>High-Resolution Side-Channel Attack Using Phase-Based Waveform Matching<br/>Cache-Collision Timing Attacks Against AES<br/>Provably Secure S-Box Implementation Based on Fourier Transform<br/>The Outer Limits of RFID Security<br/>Three-Phase Dual-Rail Pre-charge Logic<br/>Dual-Rail Random Switching Logic: A Countermeasure to Reduce Side Channel Leakage<br/>Security Evaluation of DPA Countermeasures Using Dual-Rail Pre-charge Logic Style<br/>Instruction Set Extensions for Efficient AES Implementation on 32-bit Processors<br/>NanoCMOS-Molecular Realization of Rijndael<br/>Improving SHA-2 Hardware Implementations<br/>Offline Hardware/Software Authentication for Reconfigurable Platforms<br/>Why One Should Also Secure RSA Public Key Elements<br/>Power Attack on Small RSA Public Exponent<br/>Unified Point Addition Formulæ and Side-Channel Attacks<br/>Read-Proof Hardware from Protective Coatings<br/>Path Swapping Method to Improve DPA Resistance of Quasi Delay Insensitive Asynchronous Circuits<br/>Automated Design of Cryptographic Devices Resistant to Multiple Side-Channel Attacks<br/>Challenges for Trusted Computing<br/>Superscalar Coprocessor for High-Speed Curve-Based Cryptography<br/>Hardware/Software Co-design of Elliptic Curve Cryptography on an 8051 Microcontroller<br/>FPGA Implementation of Point Multiplication on Koblitz Curves Using Kleinian Integers |
| 600 ## - SUBJECT ADDED ENTRY--PERSONAL NAME | |
| Personal name | Computer Engineering |
| 9 (RLIN) | 42153 |
| 700 ## - ADDED ENTRY--PERSONAL NAME | |
| Personal name | Goubin, Louis |
| Relator term | Editor |
| 9 (RLIN) | 42155 |
| 700 ## - ADDED ENTRY--PERSONAL NAME | |
| Personal name | Matsui, Mitsuru |
| Relator term | Editor |
| 9 (RLIN) | 42157 |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) | |
| Source of classification or shelving scheme | Dewey Decimal Classification |
| Item type | Book |
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