Reconfigurable Computing: The Theory and Practice of FPGA Based Computation (Record no. 48456)
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| 000 -LEADER | |
|---|---|
| fixed length control field | 02502nam a2200181Ia 4500 |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION | |
| fixed length control field | 140223b2008 xxu||||| |||| 00| 0 eng d |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| International Standard Book Number | 9780123705228 |
| Terms of availability | 0.00 |
| 082 ## - DEWEY DECIMAL CLASSIFICATION NUMBER | |
| Classification number | 621.395 |
| Item number | REC |
| 100 ## - MAIN ENTRY--PERSONAL NAME | |
| Personal name | Hauck, Scott |
| 245 ## - TITLE STATEMENT | |
| Title | Reconfigurable Computing: The Theory and Practice of FPGA Based Computation |
| 260 ## - PUBLICATION, DISTRIBUTION, ETC. (IMPRINT) | |
| Place of publication, distribution, etc. | New York |
| Name of publisher, distributor, etc. | Elsevier Science Inc. |
| Date of publication, distribution, etc. | 2008 |
| 300 ## - PHYSICAL DESCRIPTION | |
| Extent | 908p |
| 500 ## - GENERAL NOTE | |
| General note | Part - 1: Reconfigurable Computing Hardware Reconfigurable Computing Architectures Reconfigurable Computing Systems Reconfiguration Management Part - 2: Programming Reconfigurable Systems Computer Models and System Architectures Programming FPGA Application in VHDL Compiling C for Spatial Computing Programming Streaming FPGA Applications Using Block Diagrams in Simulink Stream Computations Organizaed for Reconfigurable Execution Programming Data Parallel FPGA Applications Using the SIMD/Vector Model Operating System Support for Reconfigurable Computing The JHDL Design and Debug System Part - 3: Mapping Designs to Reconfigurable Platforms Technology Mapping FPGA Placement Placement for General-Purpose FPGAs Datapath Composition Specifying Circuit Layout on FPGAs PathFinder: A Negotiation-Based, Performance-Driven Router for FPGAs Retiming, Repipelining, and C-slow Retiming Configuration Bisstream Generation Fast Compilation Techniques Part - 4: Application Development Implementing Applications with FPGAs Instance-Specific Design Precision Analysis for Fixed-point Computation Distributed Arithmetic CORDIC Architectures for FPGA Computing Hardware/Software Partitioning Part - 5: Case Studies of FPGA Applications SPIHT Image Compression Automatic Target Recognition Systems on Reconfigurable Devices Boolean Satisfiability: Creating Solvers Optimized for Specific Problem Instances Multi-FPGA Systems: Logic Emulation The Implications of Floating Point for FPGAs Finite Difference Time Domain: A Case Study Using FPGAs Evolvable FPGAs Network Packet Processing in Reconfigurable Hardware Active Pages: Memory-Centric Computation Part - 6: Theoretical Underpinnings and Future Directions Theoretical Underpinnings Defect and Fault Tolerance Reconfigurable Computing and Nanoscale Architecture |
| 600 ## - SUBJECT ADDED ENTRY--PERSONAL NAME | |
| Personal name | Computer Engineering |
| 700 ## - ADDED ENTRY--PERSONAL NAME | |
| Personal name | DeHon, Andre |
| 890 ## - | |
| -- | USA |
| 995 ## - RECOMMENDATION 995 [LOCAL, UNIMARC FRANCE] | |
| -- | REC |
| -- | 007274 |
| -- | CEE-PG0 |
| -- | 2674.17 |
| -- | 0 |
| -- | 049 |
| -- | IN221 |
| -- | 0 |
| -- | 0.00 |
| -- | 3613.74 26% |
| -- | 20080605 |
| -- | 01 |
| -- | C |
| -- | 20080724 |
| -- | Kushal Books |
| -- | Reference |
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