VLSI Test Principles and Architecture Design for Testability (Record no. 49262)

MARC details
000 -LEADER
fixed length control field 01081nam a2200193Ia 4500
003 - CONTROL NUMBER IDENTIFIER
control field OSt
005 - DATE AND TIME OF LATEST TRANSACTION
control field 20210924145938.0
008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION
fixed length control field 140223b2006 xxu||||| |||| 00| 0 eng d
020 ## - INTERNATIONAL STANDARD BOOK NUMBER
International Standard Book Number 9780123705976
Terms of availability 0.00
040 ## - CATALOGING SOURCE
Transcribing agency
082 ## - DEWEY DECIMAL CLASSIFICATION NUMBER
Classification number 621.395
Item number VLS
100 ## - MAIN ENTRY--PERSONAL NAME
Personal name Wang, Laung Terng
9 (RLIN) 56075
245 ## - TITLE STATEMENT
Title VLSI Test Principles and Architecture Design for Testability
260 ## - PUBLICATION, DISTRIBUTION, ETC. (IMPRINT)
Place of publication, distribution, etc. San Francisco
Name of publisher, distributor, etc. Morgan Kaufmann Publishers
Date of publication, distribution, etc. 2006
300 ## - PHYSICAL DESCRIPTION
Extent 777p
500 ## - GENERAL NOTE
General note Introduction Design for Testability Logic and Fault Simulation Test Generation Logic Built in Self Test Test Compression Logic Diagnosis Memory Testing and Built In Self Test Memory Diagnosis and Built In Self Repair Boundary Scan and Core Based Testing Analog and Mixed Signal Testing Test Technology Trends in the Nanometer Age
600 ## - SUBJECT ADDED ENTRY--PERSONAL NAME
Personal name Electronic Engineering
9 (RLIN) 56076
700 ## - ADDED ENTRY--PERSONAL NAME
Personal name Wen, Xiaoqing
9 (RLIN) 56077
700 ## - ADDED ENTRY--PERSONAL NAME
Personal name Wen, Cheng Wen
9 (RLIN) 56078
942 ## - ADDED ENTRY ELEMENTS (KOHA)
Source of classification or shelving scheme Dewey Decimal Classification
Koha item type Book

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