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Verification Techniques for System Level Design
Material type:
TextPublication details: Morgan Kaufman Publications New Delhi 2008Description: 240pISBN: - 9780123706164
- 621.3815 FUJ
| Item type | Current library | Item location | Collection | Call number | Status | Date due | Barcode | Item holds | |
|---|---|---|---|---|---|---|---|---|---|
Reference Book
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NIMA Knowledge Centre | 6th Floor Silence Zone | Reference | 621.3815 FUJ (Browse shelf(Opens below)) | Not For Loan | T0048405 |
Total holds: 0
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| 621.3815 EXP Experiments with Digital ICs: vol. 1 | 621.3815 FIN FinFETs and other Multi Gate Transistors | 621.3815 FLO Electronic Devices | 621.3815 FUJ Verification Techniques for System Level Design | 621.3815 GRA Bioelectronics Handbook: MOSFETs, Biosensors and Neurons | 621.3815 GUP SPARK: A Parallelizing Approach to the High-Level Synthesis of Digital Circuits | 621.3815 HAS The Art of Analog Layout |
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