TY  - BOOK
AU  - Saxena, Prashant
AU  - Sapatnekar, Sachin S.
AU  - Shelar, Rupesh S.
TI  - Routing Congestion in VLSI Circuits: Estimation and Optimization
SN  - 9780387300375
U1  - 621.395 
PY  - 2007///
CY  - New York
PB  - Springer Science+Business Media, Inc
KW  - Electronic Engineering
N1  - Part - 1: The Origins of Congestion An Introduction to Routing Congestion Part - 2: The Estimation of Congestion Placement-Level Metrics for Routing Congestion Synthesis-Level Metrics for Routing Congestion Part - 3: The Optimization of Congestion Congestion Optimization during Interconnects Synthesis and Routing Congestion Optimization during Placement Congestion Optimization during Technology Mapping and Logic Synthesis Congestion Implications of High Level Design
ER  -