TY  - BOOK
AU  - Hsieh, Harry
AU  - Sangiovanni-Vincentelli, Alberto
AU  - Balarin, Felice
TI  - Synchronous Equivalence: Formal Methods for Embedded Systems
SN  - 9780792372622
U1  - 004.16 
PY  - 2001///
CY  - New York
PB  - Kluwer Academic / Plenum Publishers
KW  - Computer Engineering
N1  - Introduction The Polis Codesign Framework Codesign Finite State Machines Formal Verification of CFSM Specifications Synchronous Equivalence Static Equivalence Analysis Communication Analysis Refining Communication Analysis Conclusions and Future Directions
ER  -