TY  - BOOK
AU  - Cavanagh, Joseph
TI  - Verilog HDL: Digital Design and Modeling
SN  - 9781420051544
U1  - 621.392 
PY  - 2007///
CY  - Boca Raton
PB  - CRC Press
KW  - Electronic Engineering
N1  - Introduction Overview Language Elements Expressions Gate Level Modeling User Defined Primitives Dataflow Modeling Behavioral Modeling Structural Modeling Tasks and Functions Additional Design Examples Appendix: Event Queue Verilog Project Procedure Answers to Select Problems
ER  -