TY  - BOOK
AU  - Wang, Laung Terng
AU  - Wen, Xiaoqing
AU  - Wen, Cheng Wen
TI  - VLSI Test Principles and Architecture Design for Testability
SN  - 9780123705976
U1  - 621.395 
PY  - 2006///
CY  - San Francisco
PB  - Morgan Kaufmann Publishers
KW  - Electronic Engineering
N1  - Introduction Design for Testability Logic and Fault Simulation Test Generation Logic Built in Self Test Test Compression Logic Diagnosis Memory Testing and Built In Self Test Memory Diagnosis and Built In Self Repair Boundary Scan and Core Based Testing Analog and Mixed Signal Testing Test Technology Trends in the Nanometer Age
ER  -