Design of a Low Voltage, Low Power and High Speed CMOS Comparator by Vijay Gopalbhai Savani

Guided by: Dr. N. M. Devashrayee With Synopsis and CD 11EXTPHDE69

ABSTRACT:
Analog-to-digital converters (ADCs) and Digital-to-Analog converters (DACs) are key
components of modern microelectronics applications where an interface between the analog
world and the progressive digital signal processing world is needed. They are found in an
extensive range of devices in consumer electronics, medical equipment, communication and
instrumentation applications, and current growing areas (e.g. Internet of Things (IoT), all
portable systems in today’s life, and wearable devices etc.) just to name a few. With the fast
development of CMOS technology, more and more signal processing circuits and building
blocks are implemented in the digital domain for lower cost, lower power consumption,
high-speed, higher yield, and higher re-configurability. To minimize production steps and
the cost of the final product, several functional circuit blocks are combined into one chip and
form a System on a Chip (SoC). It is common to implement digital and analog blocks into
one chip with additional ADCs or DACs.
The basic building blocks of an ADCs and DACs consist of analog circuits such as voltage
reference, operational amplifiers as well as mixed signal circuits such as comparators. The
comparator is also known as 1-bit ADC and for that reason, it is mostly used in abundance
in ADCs. Besides ADCs and DACs, the comparator has many other applications such as
VLSI logic circuits, memory, relaxation oscillators, null detector, zero-crossing detectors,
peak detectors, switching power regulators, high-speed wireless and wireline
communication systems, and many more. This has generated a great demand for high-speed,
low-power, and low-voltage comparator that can be realized in a mainstream deepsubmicron
Complementary Metal Oxide Semiconductor (CMOS) technology. The
requirement of bandwidth is also increasing day by day and almost all lower bands are
already occupied. The design of ADCs and ultimately the comparator, which work on higher
frequencies are needed in the modern world. The conversion speed of converter is restricted
by the decision-making response time of the comparator. As the comparator is one of the
blocks, which limits the speed of the converter, its optimization is of utmost importance. Not
only the speed, but lower power with low supply voltage has emerged as a principal theme
in today's electronics industry. Reduction of power consumption makes a device more
reliable and efficient. As the scaling of CMOS technology continues, the supply voltage gets
lower and it inherently limits the maximum input voltage swing. In ultra-deep sub-micron CMOS technology, the threshold voltage of the devices is not
scaled down at the same rate as supply voltage and the technology. Hence, it presents many
challenges and problem to design a comparator in sub-micron technology at low-supply
voltage.
The requirements have fostered research in two main areas to provide the solutions namely,
technological solution and solution using architectural modification. The research in the
thesis is focused on the second solution i.e. architectural modification. There are classically
two types of comparators reported in the literature viz. continues time (without clock) and
discrete time (clocked). The demanding need of ultra-high speed, area efficient and power
optimized ADCs forces towards the exploration and usage of the clocked regenerative
comparator to minimize the power, area and maximize the speed.
In this research, a novel fully dynamic latched comparator with high-speed, low-power
consumption and optimized die area compared to the conventional dynamic latch
comparators is proposed. Design considerations for comparator are also discussed in the
thesis. Based on the study, a new reset technique – shared charge logic, for the dynamic
latched comparator is proposed. In this technique, a pass transistor is used in the latch stage
to share the charge between two output terminals of the comparator during the reset phase.
The simulation is carried out in 90nm CMOS technology using Virtuoso tool. Besides,
proposed design the thesis provides a comprehensive review, analysis and implementation
for a variety of conventional (traditional) dynamic latched comparator designs along with
proposed comparator- in terms of speed, power, area, power delay product (PDP), and other
performance parameters. Various parametric variations (viz. dependence on input commonmode
voltage, input differential voltage, etc.) are also carried out and the results are
presented for the proposed comparator along with the referred comparator. Systematic and
random variations in process parameters, supply voltage, and temperature are posing a major
challenge to the future high performance VLSI design. Using Monte Carlo simulations, the
effect of process variation is studied. Also, systematic and random variations are observed
using simulation results. With a supply voltage of 1 V, at 1 GHz of frequency, the proposed comparator results in a
delay of 51.76 ps while consuming 32.62 μW of power. The proposed comparator has the
lowest PDP and energy per conversion, which is 1.69 fJ and 32.6 fJ respectively. The
comparator has less offset voltage as well as higher common-mode voltage range. It is less
sensitive to input differential voltage variation for the delay (delay/log(ΔVdiff)). The
percentage improvement in terms of delay for the proposed comparator is 63.02 %, 40.65
%, 40.46 %, and 44.51 % respectively as compared to the conventional (referred)
comparators viz. single tail, double-tail, modified double-tail and two stage dynamic latched
comparators. It is -13.24 %, 60.64 %, 372.41 %, and 75.35 % in terms of power consumption
as compared to referred architectures respectively. The post layout results of all the
comparators are also obtained. In 90nm CMOS technology, the proposed comparator
provides the maximum sampling frequency of 3.9 GHz at the 1 V supply voltage. Finally,
all the obtained results are compared with state of art architectures reported in the literature
in terms of their performance parameters and Figure of Merit (FoM). The results demonstrate
the potential of new proposed comparator architecture for high-speed, low-power, and lowvoltage
applications.