000			ngm a22 7a 4500
999			_c115918 _d115918
008			190222b ||||| |||| 00| 0 eng d
082			_aTT000067 _bDHA
100			_aDhare, Vaishali Hitesh _935804
245			_aNovel Defect Modeling and Development of ATPG For combinational QCA Circuits _cby Vaishali Hitesh Dhare
260			_aAhmedabad _bNirma Institute of Technology _c2018
300			_a170p Ph. D. Thesis with Synopsis and CD
500			_aGuided by: Dr. Usha Sandeep Mehta With Synopsis and CD 13EXTPHDE102 ABSTRACT: Although the current Complementary Metal Oxide Semiconductor (CMOS) silicon technology is ruling the semiconductor industry for almost four and half decades, the scaling of it will reach its fundamental limit in the near future. As a result, several new devices for computation are being explored to extend the historical IC scaling and to sustain the performance gain beyond CMOS scaling. The International Technology Roadmap for Semiconductors (ITRS) 2015 describes the \Beyond CMOS" in length and according to it, Quantum-dot Cellular Automata (QCA) is the transistor less computation paradigm and viable candidate for next generation device technology. Since QCA has extremely small geometry; at molecular scale, it is very natural that this technology may have more and dierent manufacturing defects and faults compared to the existing CMOS technology. Hence, whatever defect types and fault models are available in CMOS technology, beyond that, new types of defects and corresponding new fault models will be necessary to test such circuits. Further, advanced algorithms for test generation including this new fault models are required to be developed. In this work, the basics of QCA, its implementation, fabrication and basic devices are studied. Also, QCA related possible defects are surveyed, studied and analyzed using existing QCA tools at the logic and layout level. Similar to CMOS IC technology, QCA circuit implementation also requires a mature set of Electronic Design Automation (EDA) tools like simulator, synthesizer etc. Therefore, available QCA tools for dierent abstraction levels of design are studied. It is perceived that, no open source and low cost commercial synthesis tools are available. Considering synthesis as important process and requirement of synthesized QCA circuits for further test development, synthesis method: QSynthesizer is proposed. It is observed that the QCA defects like cell missing, additional cell, cell misalignment cell displacement and cell rotation aects the functionality of QCA devices. The literature is available for Single Missing Cell (SMC) defect. Here, the novel Multiple Missing Cells (MMC) defect modeling is proposed and its corresponding stuck at fault sets are identied and it is shown that these faults are not covered by SMC fault models. The proposed defect modeling is backed by the extensive simulation and kink energy based mathematical analysis. Further, Hardware Description Language (HDL)-Verilog model for QCA devices are developed to activate the fault models caused by the MMC defect at the logic level. Further, testing properties are proposed for the fault models caused by the MMC defect in main QCA logic primitive Majority Voter (MV), MV as AND (MV AND) and MV as OR (MV OR) gates to make test generation process easy and ecient. The test vector set of conventional stuck at faults is not sucient to detect the faults caused by the MMC defect. Therefore, both the fault models are considered in this work for the test generation. Further, Sandia Controllability and Observability Analysis Program (SCOAP) testability measures for MV is extended for MV based circuits which is further used for decision making in test pattern generator algorithms. The extension of basic Automatic Test Pattern Generator (ATPG) specifically targeting QCA MV properties is proposed. Subsequently, extended FAN (A Fanout Oriented) based ATPG for combinational QCA circuits: FANQ is proposed which detects the conventional s-a-0, s-a-1, fault models related to SMC as well as MMC. The proposed FANQ ATPG uses the MV specic testing properties and extended testability measures. The Hamming distance based compaction is performed to reduce the number of test vectors. At last, generated test vectors by FANQ ATPG are validated at layout level to confirm the detection of multiple missing cells defect.
856			_uhttp://repository.nirmauni.ac.in/jspui/handle/123456789/8360 _zInstitute Repository (Campus Access)
942			_2ddc _cTH