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082			_aTT000101 _bPOP
100			_aPopat, Jayesh _989963
245			_aCountermeasures against Test Infrastructure based attacks on AES Circuits and Trojans _cby Jayesh Popat
260			_aAhmedabad _bNirma Institute of Technology _cJune 2020
300			_a119p Ph. D. Thesis with Synopsis and CD
500			_aGuided by: Dr Usha Mehta With Synopsis and CD 13EXTPHDE108 ABSTRACT: In the era of Information and Communication Technology, the user information or data may take electronic form. The security of such user information from malicious intentions is a prime concern nowadays. Cryptography is used for securing the data by using algorithms in such a way that only authorized parties can access it. Cryptography goals can easily be achieved by the most widely used encryption algorithm Advanced Encryption Standard (AES). AES is a mathematically unbreakable algorithm. However, AES hardware implementation is vulnerable to attacks and secret data stored can be leaked. Therefore, Hardware Security and Trust of such cryptohardware are critically important. Hardware Security normally deals with securing the private data stored in the crypto-hardware. Hardware Trust generally aims at the design and fabrication of hardware. Hardware Trust can be violated by inserting Hardware Trojans during the design or manufacturing steps of the IC life cycle. By definition, Hardware Trojan is any addition or modification to a circuit or a system with “malicious intention”. The thesis investigates different types of hardware trojans and their state-of-the-art detection schemes in detail. Further, the novel transition probabilistic technique for Hardware Trojan detection is proposed. Experimental results demonstrate the effectiveness of the proposed scheme on various ISCAS’85 benchmark circuits. Hardware Security can be violated by attacking the AES hardware and recovering the secret key. When implemented in hardware, the most widely used scan-chains and other test infrastructure are incorporated with AES for detecting manufacturing defects after fabrication. As found generally, these scan-chains and test compression hardware are being exploited by the attacker to retrieve the secret encryption key of AES cipher. The most commonly cited test infrastructure-based attacks are the Differential Scan Attack (DSA) and Test Mode Only (TMO) attack. In this work, the basics of the AES algorithm and its state-of-the-art attacks as well as countermeasures are surveyed, studied and analyzed. As a proof of concept, it is demonstrated that with DSA as well as TMO, the secret key is recovered in case of normal AES and AES with Response Compactors (X-Tolerant and Multiple Input Signature Register). State-of-art countermeasures have area and test time limitations. Some of them are only capable of preventing DSA and others are capable of only TMO attacks. There is a high need for unified countermeasure which can thwart both attacks and should have less overheads as well as be easily integrated into the current SoC integration flow. The proposed countermeasure, Modular Exponentiation Secure Scheme (ME-SS) is based on a one-way function. The software and hardware implementation of the proposed countermeasure is included in detail. Experimental results and statistical analysis show that the proposed countermeasure is improving the security in the case of DSA as well as TMO as compared to the recently published countermeasure. It is further shown that the time and area overheads are comparatively less. To further improve the security, the novel Hash function based Secure Scheme (HSS) is proposed. This scheme is improving the security against DSA and TMO attacks compared to the recently published countermeasure as well as the proposed ME-SS countermeasure at the cost of a marginal increase in area and test time compared to previously proposed ME-SS.
856			_uhttps://repository.nirmauni.ac.in/jspui/handle/123456789/10607 _zInstitute Repository (Campus Access)
856			_zShodhganga _uhttp://shodhganga.inflibnet.ac.in/handle/10603/384347
942			_2ddc _cTH
999			_c138693 _d138693