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| 100 | _aLee, Sunggu | ||
| 245 | _aDigital Logic Design: Using Verilog, State Machines, and Synthesis for FPGAs | ||
| 260 |
_aNew Delhi _bCengage Learning Pvt. Ltd. _c2003 |
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| 300 | _a324p | ||
| 600 | _aElectronic Engineering | ||
| 890 | _aIndia | ||
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