000			01244nam a2200193Ia 4500
008			140223b2007 xxu||||| |||| 00| 0 eng d
020			_a9780387300375 _c0.00
082			_a621.395 _bSAX
100			_aSaxena, Prashant
245			_aRouting Congestion in VLSI Circuits: Estimation and Optimization
260			_aNew York _bSpringer Science+Business Media, Inc _c2007
300			_a248p
500			_aPart - 1: The Origins of Congestion An Introduction to Routing Congestion Part - 2: The Estimation of Congestion Placement-Level Metrics for Routing Congestion Synthesis-Level Metrics for Routing Congestion Part - 3: The Optimization of Congestion Congestion Optimization during Interconnects Synthesis and Routing Congestion Optimization during Placement Congestion Optimization during Technology Mapping and Logic Synthesis Congestion Implications of High Level Design
600			_aElectronic Engineering
700			_aSapatnekar, Sachin S.
700			_aShelar, Rupesh S.
890			_aUSA
995			_ASAX _B007542 _CECT-NIT _D5102.56 _E0 _F049 _GIN294 _H0 _I0.00 _J7136.45 28.5% _L20080811 _M07 _UC _W20080821 _XKushal Books _ZReference
999			_c40864 _d40864