000			00910nam a2200169Ia 4500
008			140223b2004 xxu||||| |||| 00| 0 eng d
020			_a9781402077210 _c0.00
082			_a621.38150285514 _bADV
100			_aDrechsler, Rolf
245			_aAdvanced Formal Verification
260			_aBoston _bKluwer Academic Publishers _c2004
300			_a249p
500			_aIntroduction What Sat Solvers can and cannot do Advancements in Mixed BDD and SAT Techniques Equivalence Checking of Arithmetic Circuits Application of Property Checking and Underlying Techniques Assertion Based Verification Formal Verification for Nonlinear Analog Systems
600			_aElectronic Engineering
890			_aUK
995			_AADV _B003186 _CECE-PG0 _D6240.00 _E0 _F049 _G087918 _H0 _I0.00 _J4524.00 27.5% _L20050318 _M02 _UC _W20050527 _XHimanshu Book Co. _ZReference
999			_c44204 _d44204