000			01221nam a2200169Ia 4500
008			140223b2010 xxu||||| |||| 00| 0 eng d
020			_a9781439811245 _c0.00
082			_a004.01513 _bCAV
100			_aCavanagh, Joseph
245			_aComputer Arithmetic and Verilog HDL Fundamentals
260			_aBoca Raton _bCRC Press _c2010
300			_a951p
500			_aNumber Systems and Number Representations Logic Design Fundamentals Introduction to Verilog HDL Fixed Point Addition Fixed Point Subtraction Fixed Point Multiplication Fixed Point Division Decimal Subtraction Decimal Multiplication Decimal Division Floating Point Addition Floating Point Subtraction Floating Point Multiplication Floating Point Division Additional Floating Point Topics Additional Topics in Computer Arithmetic Appendix - A: Verilog HDL Designs for Select Logic Function Appendix - B: Event Queue Appendix - C: Verilog HDL Project Procedure Appendix - D: Answers to Select Problems
600			_aElectronic Engineering
890			_aUK
995			_ACAV _B010070 _CECT-NIT _D4694.99 _E0 _F049 _GIN891 _H0 _I0.00 _J6854.00 31.5% _L20110101 _M16 _UC _W20110125 _XKushal Books _ZReference
999			_c44984 _d44984