000			01510nam a2200181Ia 4500
008			140223b1999 xxu||||| |||| 00| 0 eng d
020			_a9780824719241 _c0.00
082			_a621.3822 _bDIG
100			_aParhi, Keshab K.
245			_aDigital Signal Processing for Multimedia Systems
260			_aNew York _bMarcel Dekker, Inc. _c1999
300			_a855p
500			_aMultimedia Signal processing Systems Video Compression System Synchronization Digital Versatile Disk High-Speed Data Transmission over Twisted Pair Channels Cable Modems Wireless Communication Systems Programmable DSPs RISC, Video and Media DSPs Wireless Digital Signal Processors Motion Estimation System Design Wavelet VLSI Architecture DCT Architecture Lossless Coders Viterbi Decoders: High Performance Algorithms and Architectures A Review of Watermarking Principles and Practices Systolic RLS Adaptive Filtering Pipelined RLS for VLSI: STAR-RLS Filters Division and Square Root Finite Field Arithmetic Architecture CORDIC Algorithms and Architecture Advanced Systolic Design Low Power CMOS VLSI Design Power Estimation Approaches System Exploration for Custom Low Power Data Storage and Transfer Hardware Description and Synthesis of DSP System
600			_aElectronic Engineering
700			_aNishitani, Takao
890			_aUSA
995			_ADIG _C- _D8716.50 _E0 _F049 _G798 _H0 _I0.00 _J _UC _W20000111 _XResearchco Book Centre _ZReference
999			_c45358 _d45358