| 000 | 01004nam a2200169Ia 4500 | ||
|---|---|---|---|
| 008 | 140223b2005 xxu||||| |||| 00| 0 eng d | ||
| 020 |
_a9780131433472 _c0.00 |
||
| 082 |
_a621.39 _bLAM |
||
| 100 | _aLam, William K. | ||
| 245 | _aHardware Design Verification: Simulation and Formal Method-Based Approaches | ||
| 260 |
_aNew York _bPrentice Hall _c2005 |
||
| 300 | _a585p | ||
| 500 | _aAn Invitation to Design Verification Coding for Verification Simulator Architectures and Operations Test Bench Organization and Design Test Scenarios, Assertions, and Coverage Debugging Process and Verification Cycle Formal Verification Preliminaries Design Diagrams, Equivalence Checking, and Symbolic Simulation Model Checking and Symbolic Computation | ||
| 600 | _aElectrical Engineering | ||
| 890 | _aUSA | ||
| 995 |
_ALAM _B005126 _CECE-PG0 _D3628.99 _E0 _F049 _G092350 _H0 _I0.00 _J5005.50 27.5% _L20061111 _M01 _UC _W20070116 _XHimanshu Book Co. _ZReference |
||
| 999 |
_c46601 _d46601 |
||