000			01248nam a2200181Ia 4500
008			140223b2008 xxu||||| |||| 00| 0 eng d
020			_a9780387764863 _c0.00
082			_a621.3950287 _bTEH
100			_aTehranipoor, Mohammad
245			_aNanometer Technology Designs High-Quality Delay Tests
260			_aNew York _bSpringer Science+Business Media, Inc _c2008
300			_a281p
500			_aIntroduction At speed Test Challenges for Nanometer Technology Designs Local At-Speed Scan Enable Generation using Low - Cost Testers Enhanced Launch off Capture Hybrid Scan Based Transition Delay Test Avoiding Functionally Untestable Faults Screening Small Delay Defects Faster Than At Speed Test Considering IR-Drop Effects IR-Drop Tolerant At speed Test Pattern Generation Pattern Generation for Power Supply Noise Analysis Delay Fault Testing in Presence of Maximum Crosstalk Testing SoC Interconnects for Signal Integrity Index
600			_aElectronic Engineering
700			_aAhmed, Nisar
890			_aUSA
995			_ATEH _B008927 _CECC-PG0 _D2944.21 _E0 _F049 _G4989 _H0 _I0.00 _J4089.18 28% _L20091216 _M01 _UC _W20100118 _XMahajan Book Depot _ZReference
999			_c47708 _d47708