000			00965nam a2200145Ia 4500
008			140223b1993 xxu||||| |||| 00| 0 eng d
020			_c0.00
082			_a621.395 _bPRO
245			_aProgrammable Logic Devices Databook and Design Guide
260			_aCalifornia _bNational Semiconductor Corporation _c1993
500			_aProduct Line Overview Part - 1: PLD Design and Fabrication Part - 2: Low Density GAL and PAL Devices GAL and PAL Datasheets GAL and PAL Application Examples GAL and PAL Application Notes Part - 3: High Density MAPL Family MAPL Datasheets MAPL Application Examples MAPL Application Notes Part - 4: PLD Development Tools Part - 5: Appendices/Physical Dimensions Appendix - A: Boolean Logic Review Appendix - B: Theory of PLD Testing Physical Dimensions
600			_aElectronic Engineering
890			_aUSA
995			_APRO _C- _D600.00 _E0 _F049 _G15908 _H0 _I0.00 _UC _W19971118 _XBooks India _ZReference
999			_c48347 _d48347