000			02502nam a2200181Ia 4500
008			140223b2008 xxu||||| |||| 00| 0 eng d
020			_a9780123705228 _c0.00
082			_a621.395 _bREC
100			_aHauck, Scott
245			_aReconfigurable Computing: The Theory and Practice of FPGA Based Computation
260			_aNew York _bElsevier Science Inc. _c2008
300			_a908p
500			_aPart - 1: Reconfigurable Computing Hardware Reconfigurable Computing Architectures Reconfigurable Computing Systems Reconfiguration Management Part - 2: Programming Reconfigurable Systems Computer Models and System Architectures Programming FPGA Application in VHDL Compiling C for Spatial Computing Programming Streaming FPGA Applications Using Block Diagrams in Simulink Stream Computations Organizaed for Reconfigurable Execution Programming Data Parallel FPGA Applications Using the SIMD/Vector Model Operating System Support for Reconfigurable Computing The JHDL Design and Debug System Part - 3: Mapping Designs to Reconfigurable Platforms Technology Mapping FPGA Placement Placement for General-Purpose FPGAs Datapath Composition Specifying Circuit Layout on FPGAs PathFinder: A Negotiation-Based, Performance-Driven Router for FPGAs Retiming, Repipelining, and C-slow Retiming Configuration Bisstream Generation Fast Compilation Techniques Part - 4: Application Development Implementing Applications with FPGAs Instance-Specific Design Precision Analysis for Fixed-point Computation Distributed Arithmetic CORDIC Architectures for FPGA Computing Hardware/Software Partitioning Part - 5: Case Studies of FPGA Applications SPIHT Image Compression Automatic Target Recognition Systems on Reconfigurable Devices Boolean Satisfiability: Creating Solvers Optimized for Specific Problem Instances Multi-FPGA Systems: Logic Emulation The Implications of Floating Point for FPGAs Finite Difference Time Domain: A Case Study Using FPGAs Evolvable FPGAs Network Packet Processing in Reconfigurable Hardware Active Pages: Memory-Centric Computation Part - 6: Theoretical Underpinnings and Future Directions Theoretical Underpinnings Defect and Fault Tolerance Reconfigurable Computing and Nanoscale Architecture
600			_aComputer Engineering
700			_aDeHon, Andre
890			_aUSA
995			_AREC _B007274 _CCEE-PG0 _D2674.17 _E0 _F049 _GIN221 _H0 _I0.00 _J3613.74 26% _L20080605 _M01 _UC _W20080724 _XKushal Books _ZReference
999			_c48456 _d48456