000			01455nam a2200193Ia 4500
008			140223b2004 xxu||||| |||| 00| 0 eng d
020			_a9781402078378 _c0.00
082			_a621.3815 _bGUP
100			_aGupta, Sumit
245			_aSPARK: A Parallelizing Approach to the High-Level Synthesis of Digital Circuits
260			_aNew York _bKluwer Academic / Plenum Publishers _c2004
300			_a233p
500			_aI. Introduction to High - Level Synthesis Introduction Survey of Previous Work Models and Representations Parallelizing High - Level Synthesis (PHLS) Our Parallelizing High - Level Synthesis Methodology Pre - Synthesis Compiler Optimizations Compiler and Synthesis Transformations Employed During Scheduling Code Transformations and Scheduling Resource Binding and Control Synthesis III. SPARK: Implementation, Scripts and De3sign Examples Design Examples Case Study: Synthesis of an Instruction Length Decoder IV. Future Directions Conclusions and Future Work V. Appendix Appendix - A: SPARK: Usage, Synthesis Scripts and Hardware Library Files Appendix - B: Sample Runs Bibliography
600			_aComputer Engineering
700			_aDutt, Nikil D.
700			_aGupta, Rajesh K.
890			_aUSA
995			_AGUP _B007884 _CCEE-PG0 _D6226.94 _E0 _F049 _G98323 _H0 _I0.00 _J8709.01 28.5% _L20081115 _M01 _UC _W20090130 _XHimanshu Book Co. _ZReference
999			_c48755 _d48755