| 000 | 00884nam a2200169Ia 4500 | ||
|---|---|---|---|
| 008 | 140223b2007 xxu||||| |||| 00| 0 eng d | ||
| 020 |
_a9781420051544 _c0.00 |
||
| 082 |
_a621.392 _bCAV |
||
| 100 | _aCavanagh, Joseph | ||
| 245 | _aVerilog HDL: Digital Design and Modeling | ||
| 260 |
_aBoca Raton _bCRC Press _c2007 |
||
| 300 | _a900p | ||
| 500 | _aIntroduction Overview Language Elements Expressions Gate Level Modeling User Defined Primitives Dataflow Modeling Behavioral Modeling Structural Modeling Tasks and Functions Additional Design Examples Appendix: Event Queue Verilog Project Procedure Answers to Select Problems | ||
| 600 | _aElectronic Engineering | ||
| 890 | _aUSA | ||
| 995 |
_ACAV _B006260 _CECE-PG0 _D2866.49 _E0 _F049 _G37542 _H0 _I0.00 _J3873.64 26% _L20071019 _M05 _UC _W20071023 _XBooks India _ZReference |
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| 999 |
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||