Routing Congestion in VLSI Circuits: Estimation and Optimization (Record no. 40864)
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| 000 -LEADER | |
|---|---|
| fixed length control field | 01244nam a2200193Ia 4500 |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION | |
| fixed length control field | 140223b2007 xxu||||| |||| 00| 0 eng d |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| International Standard Book Number | 9780387300375 |
| Terms of availability | 0.00 |
| 082 ## - DEWEY DECIMAL CLASSIFICATION NUMBER | |
| Classification number | 621.395 |
| Item number | SAX |
| 100 ## - MAIN ENTRY--PERSONAL NAME | |
| Personal name | Saxena, Prashant |
| 245 ## - TITLE STATEMENT | |
| Title | Routing Congestion in VLSI Circuits: Estimation and Optimization |
| 260 ## - PUBLICATION, DISTRIBUTION, ETC. (IMPRINT) | |
| Place of publication, distribution, etc. | New York |
| Name of publisher, distributor, etc. | Springer Science+Business Media, Inc |
| Date of publication, distribution, etc. | 2007 |
| 300 ## - PHYSICAL DESCRIPTION | |
| Extent | 248p |
| 500 ## - GENERAL NOTE | |
| General note | Part - 1: The Origins of Congestion An Introduction to Routing Congestion Part - 2: The Estimation of Congestion Placement-Level Metrics for Routing Congestion Synthesis-Level Metrics for Routing Congestion Part - 3: The Optimization of Congestion Congestion Optimization during Interconnects Synthesis and Routing Congestion Optimization during Placement Congestion Optimization during Technology Mapping and Logic Synthesis Congestion Implications of High Level Design |
| 600 ## - SUBJECT ADDED ENTRY--PERSONAL NAME | |
| Personal name | Electronic Engineering |
| 700 ## - ADDED ENTRY--PERSONAL NAME | |
| Personal name | Sapatnekar, Sachin S. |
| 700 ## - ADDED ENTRY--PERSONAL NAME | |
| Personal name | Shelar, Rupesh S. |
| 890 ## - | |
| -- | USA |
| 995 ## - RECOMMENDATION 995 [LOCAL, UNIMARC FRANCE] | |
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| -- | 07 |
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| -- | Kushal Books |
| -- | Reference |
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