Computer Arithmetic and Verilog HDL Fundamentals (Record no. 44984)
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000 -LEADER | |
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fixed length control field | 01221nam a2200169Ia 4500 |
008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION | |
fixed length control field | 140223b2010 xxu||||| |||| 00| 0 eng d |
020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
International Standard Book Number | 9781439811245 |
Terms of availability | 0.00 |
082 ## - DEWEY DECIMAL CLASSIFICATION NUMBER | |
Classification number | 004.01513 |
Item number | CAV |
100 ## - MAIN ENTRY--PERSONAL NAME | |
Personal name | Cavanagh, Joseph |
245 ## - TITLE STATEMENT | |
Title | Computer Arithmetic and Verilog HDL Fundamentals |
260 ## - PUBLICATION, DISTRIBUTION, ETC. (IMPRINT) | |
Place of publication, distribution, etc. | Boca Raton |
Name of publisher, distributor, etc. | CRC Press |
Date of publication, distribution, etc. | 2010 |
300 ## - PHYSICAL DESCRIPTION | |
Extent | 951p |
500 ## - GENERAL NOTE | |
General note | Number Systems and Number Representations Logic Design Fundamentals Introduction to Verilog HDL Fixed Point Addition Fixed Point Subtraction Fixed Point Multiplication Fixed Point Division Decimal Subtraction Decimal Multiplication Decimal Division Floating Point Addition Floating Point Subtraction Floating Point Multiplication Floating Point Division Additional Floating Point Topics Additional Topics in Computer Arithmetic Appendix - A: Verilog HDL Designs for Select Logic Function Appendix - B: Event Queue Appendix - C: Verilog HDL Project Procedure Appendix - D: Answers to Select Problems |
600 ## - SUBJECT ADDED ENTRY--PERSONAL NAME | |
Personal name | Electronic Engineering |
890 ## - | |
-- | UK |
995 ## - RECOMMENDATION 995 [LOCAL, UNIMARC FRANCE] | |
-- | CAV |
-- | 010070 |
-- | ECT-NIT |
-- | 4694.99 |
-- | 0 |
-- | 049 |
-- | IN891 |
-- | 0 |
-- | 0.00 |
-- | 6854.00 31.5% |
-- | 20110101 |
-- | 16 |
-- | C |
-- | 20110125 |
-- | Kushal Books |
-- | Reference |
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