Nanometer Technology Designs High-Quality Delay Tests
Material type:
TextPublication details: New York Springer Science+Business Media, Inc 2008Description: 281pISBN: - 9780387764863
- 621.3950287 TEH
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Reference Book
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NIMA Knowledge Centre | 6th Floor Silence Zone | Reference | 621.3950287 TEH (Browse shelf(Opens below)) | Not For Loan | T0037542 |
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| 621.395 WOL FPGA Based System Design | 621.395 ZEI Designing with FPGAs and CPLDs | 621.3950287 NIC Power-Constrained Testing of VLSI Circuits | 621.3950287 TEH Nanometer Technology Designs High-Quality Delay Tests | 621.3950287 TRA Transistor Level Modeling for Analog / RF IC Design | 621.397 MEM Memory Data | 621.39732 BAK CMOS: Mixed Signal Circuit Design |
Introduction At speed Test Challenges for Nanometer Technology Designs Local At-Speed Scan Enable Generation using Low - Cost Testers Enhanced Launch off Capture Hybrid Scan Based Transition Delay Test Avoiding Functionally Untestable Faults Screening Small Delay Defects Faster Than At Speed Test Considering IR-Drop Effects IR-Drop Tolerant At speed Test Pattern Generation Pattern Generation for Power Supply Noise Analysis Delay Fault Testing in Presence of Maximum Crosstalk Testing SoC Interconnects for Signal Integrity Index
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