Nanometer Technology Designs High-Quality Delay Tests

By:

Tehranipoor, Mohammad

Contributor(s):

Ahmed, Nisar

Material type: Text

TextPublication details: New York Springer Science+Business Media, Inc 2008Description: 281pISBN:

9780387764863

Subject(s):

Electronic Engineering

DDC classification:

621.3950287 TEH

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Holdings
Item type	Current library	Item location	Collection	Call number	Status	Date due	Barcode	Item holds
Reference Book	NIMA Knowledge Centre	6th Floor Silence Zone	Reference	621.3950287 TEH (Browse shelf(Opens below))	Not For Loan		T0037542

Total holds: 0

Introduction At speed Test Challenges for Nanometer Technology Designs Local At-Speed Scan Enable Generation using Low - Cost Testers Enhanced Launch off Capture Hybrid Scan Based Transition Delay Test Avoiding Functionally Untestable Faults Screening Small Delay Defects Faster Than At Speed Test Considering IR-Drop Effects IR-Drop Tolerant At speed Test Pattern Generation Pattern Generation for Power Supply Noise Analysis Delay Fault Testing in Presence of Maximum Crosstalk Testing SoC Interconnects for Signal Integrity Index

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